DocumentCode
2398346
Title
Improvement of Method of the Silicic Compiling Through Discrete Optimization of Topology and Structurally-Technological Limitations of the Integrated Circuit
Author
Atamanyuk, Roman
fYear
2006
fDate
Feb. 28 2006-March 4 2006
Firstpage
436
Lastpage
437
Abstract
The improvement of method of the silicic compiling is found. This method is optimization after time -probability criteria on the planning of topology of integrated schems.
Keywords
circuit optimisation; integrated circuit technology; probability; discrete optimization; integrated circuit topology; silicic compiling; structurally-technological limitations; time-probability criteria; Circuit topology; Feeds; Joining processes; Linear programming; Minimization methods; Optimization methods; Resistance heating; Standardization; Steiner trees; Tires;
fLanguage
English
Publisher
ieee
Conference_Titel
Modern Problems of Radio Engineering, Telecommunications, and Computer Science, 2006. TCSET 2006. International Conference
Conference_Location
Lviv-Slavsko
Print_ISBN
966-553-507-2
Type
conf
DOI
10.1109/TCSET.2006.4404575
Filename
4404575
Link To Document