DocumentCode
2398450
Title
Optimization of Submicron CMOS Differential Pass-Transistor Logic
Author
Pasternak, John H. ; Salama, C. Andre T
Author_Institution
Dept. of Electr. Eng., Univ. of Toronto, Toronto, ON, Canada
fYear
1989
fDate
20-22 Sept. 1989
Firstpage
218
Lastpage
221
Abstract
Techniques for significantly enhancing the speed of CMOS differential pass-transistor logic (DPTL) are presented. Use is made of the noise immunity features of DPTL to enable signal swing reductions that result in increased speed. A novel single-phase clocking scheme using a new DPTL buffer is proposed. Experimental results are provided for a DPTL divide-by-N prescaler (1 ≤ N ≤ 64) implemented in a 0.8 μm CMOS technology.
Keywords
CMOS logic circuits; buffer circuits; integrated circuit noise; logic design; CMOS differential pass-transistor logic; DPTL buffer; noise immunity; single-phase clocking scheme; size 0.8 mum; CMOS logic circuits; CMOS technology; Circuit noise; Clocks; Degradation; Delay; Dynamic range; Logic circuits; Noise reduction; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1989. ESSCIRC '89. Proceedings of the 15th European
Conference_Location
Vienna
Print_ISBN
3-85403-101-7
Type
conf
DOI
10.1109/ESSCIRC.1989.5468086
Filename
5468086
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