A Single Chip 5 Volt 2400 Bps Modem

Author

Levy, Steriien D. ; Hurst, Paul J. ; Ju, Peicheng ; Huggins, John M. ; Cole, Christopher R.

Author_Institution

Silicon Syst. Inc., Nevada City, CA, USA

fYear

1989

fDate

20-22 Sept. 1989

Firstpage

188

Lastpage

191

Abstract

A single-chip 2400 bps modem which has been implemented in a 3.6 μm Si gate CMOS process will be described. An analog front end (AFE) and digital signal processor (DSP) are included on the IC. The transmit-side and part of the receive-side signal processing are performed in the analog domain. The DSP is dedicated to receive signal processing - timing recovery, adaptive equalization, carrier recovery/demodulation and decoding. The chip operates off a single 5 V supply, occupies 68.8 mm² and dissipates 120 mW. The design and performance of the IC will be presented.

Keywords

CMOS analogue integrated circuits; decoding; demodulation; digital signal processing chips; elemental semiconductors; equalisers; modems; radio receivers; silicon; Si; Si gate CMOS process; adaptive equalization; analog domain; analog front end; bit rate 2400 bit/s; carrier recovery/demodulation; decoding; digital signal processor; power 120 mW; receive-side signal processing; single chip modem; size 3.6 mum; timing recovery; transmit-side signal processing; voltage 5 V; Adaptive equalizers; Adaptive signal processing; Analog integrated circuits; CMOS process; Demodulation; Digital integrated circuits; Digital signal processing chips; Digital signal processors; Modems; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1989. ESSCIRC '89. Proceedings of the 15th European

Conference_Location

Vienna

Print_ISBN

3-85403-101-7

Type

conf

DOI

10.1109/ESSCIRC.1989.5468101

Filename

5468101