DocumentCode
2398945
Title
Pipelined 16k Buffer RAM with 300MHz Operating Frequency
Author
Iedel, D. Schmitt-Lands ; Hoppe, B. ; Neuendorf, G. ; Wurm, M. ; Winner, J.
Author_Institution
Corp. R&D, Siemens AG, Munich, Germany
fYear
1989
fDate
20-22 Sept. 1989
Firstpage
172
Lastpage
175
Abstract
A new pipeline architecture for fast CMOS buffer SRAMs is presented that allows operation at very high clock rates. The high speed is achieved by use of a hierarchical architecture and a memory cell with separate read and write data lines.
Keywords
CMOS digital integrated circuits; buffer circuits; logic design; random-access storage; CMOS; buffer SRAM; clock rates; frequency 300 MHz; hierarchical architecture; memory cell; read data lines; write data lines; Circuits; Clocks; Delay; Frequency; Pipelines; Proposals; Random access memory; Read-write memory; Registers; Signal generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1989. ESSCIRC '89. Proceedings of the 15th European
Conference_Location
Vienna
Print_ISBN
3-85403-101-7
Type
conf
DOI
10.1109/ESSCIRC.1989.5468115
Filename
5468115
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