A design oriented model for timing jitter/skew of Voltage-to-Time Converter (VTC) circuits

Author

Mostafa, Hassan ; Ismail, Yehea I.

Author_Institution

Electron. & Commun. Eng. Dept., Cairo Univ., Cairo, Egypt

fYear

2014

fDate

4-7 May 2014

Firstpage

1

Lastpage

6

Abstract

Time-based ADC is an essential block in designing software radio receivers because it exhibits higher speed and lower power compared to the conventional ADC, especially, at scaled CMOS technologies. In time-based ADCs, the input voltage is first converted to a pulse delay time by using a Voltage-to-Time Converter (VTC) circuit, and then the pulse delay time is converted to a digital word by using a Time-to-Digital Converter (TDC) circuit. In this paper, an analytical model for the timing jitter and skew due to noise and process variations, respectively, is proposed for the VTC circuit. The derived model is verified and compared to Monte Carlo simulations and Eldo transient noise simulations by using industrial 65-nm CMOS technology. This paper shows how the timing jitter/skew can be reduced by using circuit design knobs such as the supply voltage and the load capacitance.

Keywords

CMOS integrated circuits; analogue-digital conversion; integrated circuit noise; timing jitter; ADC skew; CMOS technology; circuit noise; design oriented model; process variation; size 65 nm; time based ADC; timing jitter; voltage-to-time converter circuits; Delays; Integrated circuit modeling; Inverters; Noise; Semiconductor device modeling; Timing jitter; Transistors; Nanometer CMOS technology; process variations; timing jitter/skew; voltage-to-time converter;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering (CCECE), 2014 IEEE 27th Canadian Conference on

Conference_Location

Toronto, ON

ISSN

0840-7789

Print_ISBN

978-1-4799-3099-9

Type

conf

DOI

10.1109/CCECE.2014.6900928

Filename

6900928