Modeling, simulation, and design methodology of the interconnect and packaging of an ultra-high speed source synchronous bus

In this paper, we describe the modeling, simulation and design methodology of the interconnect and packaging for a 400 MHz L2 level cache. Since the bus is source synchronous or “self timed”, the signal integrity, and hence the electrical performance of the package and board interconnects is a major limiter to the bus speed. To this end, we present circuit design techniques to alleviate packaging problems such as the implementation of a dynamically controlled driver impedance and edge rate. The timing equations for the source synchronous I/O bus are written in terms of the basic fundamental limitations of the silicon, package, and board processes. The interconnect performance modeling and simulation methodologies used to optimize these equations are described