Design methodology for on-chip interconnects

Author

Cases, Moiscs ; Smith, Howard ; Bowen, Michael

Author_Institution

IBM Corp., Austin, TX, USA

fYear

1998

fDate

26-28 Oct 1998

Firstpage

27

Lastpage

30

Abstract

A design methodology for on-chip interconnects which utilizes fast circuit simulator techniques to control signal coupling and transition rate degradation is described. CMOS process technology trends and their effects on interconnect performance are discussed. Critical design parameter curves are used to optimize a set of wire geometries that satisfies the electrical constraints for high density chips

Keywords

CMOS integrated circuits; circuit CAD; circuit optimisation; circuit simulation; integrated circuit design; integrated circuit interconnections; integrated circuit metallisation; CMOS process technology trends; critical design parameter curves; design methodology; electrical constraints; fast circuit simulator techniques; high density chips; interconnect performance; on-chip interconnects; signal coupling; transition rate degradation; wire geometry optimization; CMOS process; CMOS technology; Circuit simulation; Constraint optimization; Coupling circuits; Degradation; Design methodology; Design optimization; Integrated circuit interconnections; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 1998. IEEE 7th Topical Meeting on

Conference_Location

West Point, NY

Print_ISBN

0-7803-4965-2

Type

conf

DOI

10.1109/EPEP.1998.733493

Filename

733493