DocumentCode
2399722
Title
Vector extensions to the VAX architecture
Author
Bhandarkar, Dileep ; Brunner, Richard
Author_Institution
Digital Equipment Corp., Boxborough, MA, USA
fYear
1990
fDate
Feb. 26 1990-March 2 1990
Firstpage
120
Lastpage
126
Abstract
The extension of the VAX architecture to include integrated vector processing is discussed. The design goals and constraints and an overview of the resulting architecture are presented. The architecture maximizes the asynchronism between the scalar and vector processors and the parallelism within the vector processor. However, the design is consistent enough with the overall philosophy of the VAX architecture that only minimal changes to existing operating systems be required to support it.<>
Keywords
DEC computers; parallel architectures; VAX architecture; asynchronism; integrated vector processing; operating systems; parallelism; scalar processor; vector processor; Arithmetic; Concurrent computing; Memory architecture; Memory management; Registers; Vector processors;
fLanguage
English
Publisher
ieee
Conference_Titel
Compcon Spring '90. Intellectual Leverage. Digest of Papers. Thirty-Fifth IEEE Computer Society International Conference.
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-8186-2028-5
Type
conf
DOI
10.1109/CMPCON.1990.63663
Filename
63663
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