Design and Evaluation of an Integrated Digital-Analogue Filter Converter

This paper describes the design, integrated circuit implementation, and experimental evaluation of a novel building block that realizes the combined operations of digital-analogue conversion and FIR filtering (DAFIC). To maximize the advantages of both digital and analogue techniques, the circuit comprises a 4-stage digital delay line providing the input to 4 8-bit algorithmic digital-analogue converters whose gains are weighted according to the coefficients of an FIR filtering function. The circuit was implemented using a 3μm Single-Metal/Double-Poly CMOS process. Experimental results obtained from prototype chips are in good agreement with the expected theoretical behaviour of this novel building block.