Title :
Signal propagation on seamless high off-chip connectivity (SHOCC) interconnects
Author :
Afonso, S. ; Brown, W.D. ; Schaper, L.W. ; Parkerson, J.P.
Author_Institution :
Dept. of Electr. Eng., Arkansas Univ., Fayetteville, AR, USA
Abstract :
Placing long on-chip signal lines in an interconnect substrate is regarded as a solution for the long lossy line (L3) problem (Davidson et al, 1998). Modeling and simulation of SHOCC signal interconnects are described here. Simulations were carried out using a low impedance ideal driver and cascaded CMOS drivers to drive SHOCC interconnects and also typical on-chip interconnects so that a comparative study of their electrical performance could be made
Keywords :
CMOS integrated circuits; cascade networks; driver circuits; integrated circuit interconnections; integrated circuit metallisation; integrated circuit modelling; integrated circuit packaging; integrated circuit testing; losses; SHOCC interconnects; SHOCC signal interconnects; cascaded CMOS drivers; electrical performance; interconnect substrate; long lossy line problem; long on-chip signal lines; low impedance ideal driver; modeling; on-chip interconnects; seamless high off-chip connectivity interconnects; signal propagation; simulation; Conductors; Dielectric substrates; Driver circuits; Frequency; Impedance; Integrated circuit interconnections; Power system interconnection; Power system protection; Topology; Wiring;
Conference_Titel :
Electrical Performance of Electronic Packaging, 1998. IEEE 7th Topical Meeting on
Conference_Location :
West Point, NY
Print_ISBN :
0-7803-4965-2
DOI :
10.1109/EPEP.1998.733518
