Test considerations for jitter tolerance of wireline receivers

Author

DiCecco, Roberto ; Pahuta, Roman ; Holdenried, Chris ; Sadr, Sanam

Author_Institution

Semtech Snowbush IP, Toronto, ON, Canada

fYear

2014

fDate

4-7 May 2014

Firstpage

1

Lastpage

5

Abstract

A conventional jitter tolerance test methodology for high speed serial data receivers is discussed and evaluated. A Built-in Self-Test (BIST) based methodology for jitter tolerance measurement is detailed and characterized, demonstrating improved accuracy of jitter tolerance measurements of the receiver front-end and reduced complexity by using on-chip Bit Error Rate Testing. Measurements of the BIST methodology demonstrate an improvement in jitter tolerance of up to 280 mUI at a BER of 10^-12 with a 95% confidence level in a 28nm CMOS PHY operating at 10.3125-Gbps. Differences between the two methods are detailed, and difficulties associated with the conventional method are explained.

Keywords

CMOS integrated circuits; built-in self test; clock and data recovery circuits; error statistics; jitter; radio receivers; telecommunication equipment testing; BIST; CMOS PHY integrated circuit; bit rate 10.3125 Gbit/s; built-in self-test; clock and data recovery circuits; high speed serial data receivers; jitter tolerance measurement; receiver CDR testing; receiver frontend; size 28 nm; wireline receivers; Bit error rate; Built-in self-test; Clocks; Jitter; Receivers; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering (CCECE), 2014 IEEE 27th Canadian Conference on

Conference_Location

Toronto, ON

ISSN

0840-7789

Print_ISBN

978-1-4799-3099-9

Type

conf

DOI

10.1109/CCECE.2014.6900978

Filename

6900978