DocumentCode
2400136
Title
A Sea-of-Gates Architecture Based on VLSI System Design Requirements
Author
Koopman, R.J.H. ; Kerkhoff, H.G.
Author_Institution
MESA Res. Inst., Univ. of Twente, Enschede, Netherlands
fYear
1992
fDate
21-23 Sept. 1992
Firstpage
279
Lastpage
282
Abstract
This paper presents a 1.0 μm double-metal layer CMOS sea-of-gates architecture based on requirements common to the entire VLSI application area instead of a specified field. These requirements include reduction of power consumption, transparent to design flow, be able to design circuits with densities limited only by the used technology, reduce the delay of critical paths and solve complex routing problems. The results of benchmark circuits will be presented to illustrate the functionality of the architecture.
Keywords
CMOS integrated circuits; VLSI; VLSI system design requirements; benchmark circuits; circuits design; double-metal layer CMOS sea-of-gates architecture; power consumption reduction; size 1.0 mum; CMOS technology; Capacitance; Delay; Energy consumption; Integrated circuit technology; Logic design; MOSFETs; Routing; Very large scale integration; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1992. ESSCIRC '92. Eighteenth European
Conference_Location
Copenhagen
Print_ISBN
87-984232-0-7
Type
conf
DOI
10.1109/ESSCIRC.1992.5468183
Filename
5468183
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