Title :
Noise Considerations on High Density DRAMs: Problems and Solutions
Author :
Murphy, B. ; Bonner, F. ; Stecker, J. ; Reczek, W. ; Pribyl, W. ; Harter, J.
Author_Institution :
Components Group, Siemens AG, Munich, Germany
Abstract :
On-chip generated noise limits further miniaturization of DRAMs. The basis for consideration is a model including the effects of ohmic voltage drop and bond wire inductances. SPICE simulations are used to study the performance that results from chip architecture, circuit placement and circuit design. The results are verified by experimental data.
Keywords :
DRAM chips; SPICE; inductance; integrated circuit layout; integrated circuit modelling; integrated circuit noise; lead bonding; SPICE simulation; bond wire inductance; chip architecture; circuit design; circuit placement; high density DRAM; noise consideration; ohmic voltage drop; on-chip generated noise; Bonding; CMOS logic circuits; Circuit noise; Circuit synthesis; Decoding; Noise generators; RLC circuits; Rails; Voltage; Wire;
Conference_Titel :
Solid-State Circuits Conference, 1989. ESSCIRC '89. Proceedings of the 15th European
Conference_Location :
Vienna
Print_ISBN :
3-85403-101-7
DOI :
10.1109/ESSCIRC.1989.5468200
