A 54 MHz CMOS Programmable Video Signal Processor for HDTV Applications

A 54 MHz CMOS Video Processor with a systolic architecture suited for 2D symmetric FIR filtering will be reported. The circuit is a ID digital filter comprised of a control part and an array of 8 Multiplication-Accumulation cells. This processor is capable of handling 32 equivalent multiply-add operations in a sampling period as short as 18 ns. Devices can be cascaded to increase the order of the filter in both dimensions, up to 1024 stages with no truncation errors. It has been developed in a 1.2 μm CMOS technology and it dissipates less than 500 mW at a 54 MHz clock frequency.