Title :
A 16-channel Readout Chip - A new sparse data readout architecture
Author :
Murray, P. ; Lovell, M.
Author_Institution :
Rutherford Appleton Lab. (R.A.L), Didcot, UK
Abstract :
This paper describes a new architecture for performing data compression on a large matrix of parallel digital inputs, only a small proportion of which carries a logical ´I´. The system assigns a unique address to each of the active inputs (suppressing the inactive ones) and feeds them serially onto a data bus. The architecture is implemented using an array of CMOS digital signal processing ASICs, which have been designed at R.A.L, England and tested at C.E.R.N. in Geneva.
Keywords :
CMOS digital integrated circuits; application specific integrated circuits; data compression; digital readout; digital signal processing chips; sparse matrices; 16-channel readout chip; C.E.R.N; CMOS digital signal processing ASIC; data bus; data compression; parallel digital input; sparse data readout architecture; Application software; CMOS process; Data acquisition; Data compression; Digital signal processing chips; Feeds; High energy physics instrumentation computing; Laboratories; Signal design; System buses;
Conference_Titel :
Solid-State Circuits Conference, 1992. ESSCIRC '92. Eighteenth European
Conference_Location :
Copenhagen
Print_ISBN :
87-984232-0-7
DOI :
10.1109/ESSCIRC.1992.5468222
