Title :
A one megabit SRAM fabricated with 1.2 μ technology
Author :
Warren, Ben ; Richardson, Wayne ; Kanegawa, Keigi ; Arnell, Cliff ; Shimizu, Hiroshi ; Nakai, K. ; Hara, S. ; Ichiba, K.
Author_Institution :
Inova Microelectron., Santa Clara, CA, USA
Abstract :
A monolithic 1-Mb static random-access memory (SRAM) with a typical access time of 55 ns, fabricated using 1.2- μm CMOS technology, is described. The product incorporates a design approach that permits the manufacture of next-generation products (0.8- μm 1-Mb SRAMs) on current, well-understood production processes. The yield history using this technique supports wafer-level repetitive structures such as memory, or processor/memory combinations. Supporting actual yield data are presented. The product is constructed of many small memories that are fabricated through metal 1, then tested and laser repaired and subsequently interconnected, using a nondiscretionary metal 2 layer, into a much larger memory system
Keywords :
CMOS integrated circuits; VLSI; integrated memory circuits; random-access storage; 0.8 micron; 1 Mbit; 1.2 micron; 55 ns; CMOS technology; SRAM; access time; laser repaired; next-generation products; static random-access memory; wafer-level repetitive structures; yield history; CMOS integrated circuits; CMOS technology; History; Manufacturing processes; Monolithic integrated circuits; Production; Random access memory; Redundancy; System testing; Wafer scale integration;
Conference_Titel :
Wafer Scale Integration, 1989. Proceedings., [1st] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-9901-9
DOI :
10.1109/WAFER.1989.47535
