Edge and extreme edge wafer manufacturing on 200 mm wafer: Methodology, yield challenges, cost effective solutions, limitations

In this paper we present the methodology for the extreme edge of the wafer qualification for aluminium 0.22 mum embedded EEPROM technology, as edge exclusion has moved to 2 mm. Yield challenges, cost effective solutions for the yield edge detractors, process monitoring enhancement and limitations are investigated. We discussed through examples process uniformity for CMP (chemical mechanical polishing), etch or litho processes that we have had to solve. Solutions and limitations are described for nitride residual during planarization process, spacer etch process, and shorts within connection module. Monitoring scheme is evaluated for different techniques with parameters as cost efficiency or time response. This grid has been applied to the monitoring of the improved process with a wide range of confidence level which corresponds to a real difficulty for monitoring the edge and extreme edge of the wafer.