Hardware implementation of a real-time genetic algorithm for adaptive filtering applications

Genetic algorithms are increasingly being used to address adaptive filtering problems. The interest lies in their ability to find the global solutions for linear and nonlinear problems. However, all the work available in the literature use software implementations running on sequential processors. This work proposes a hardware architecture of a real-time genetic algorithm for adaptive filtering applications. Specifically designed genetic operators are proposed to improve processing performance and robustness to the quantization effect, making low bit-wordlength fixed-point arithmetic implementation possible, which permit hardware cost saving. The proposed architecture is modeled in VHDL and implemented in FPGA using 6-bits wordlength, addressing linear and nonlinear auto regressive moving average (ARMA) model parameters identification problem. The implementation experiments show high signal processing performance and low resources cost.