DocumentCode :
2401535
Title :
Design Considerations for Neutral Point Clamped Converters
Author :
Bendre, Ashish ; Cuzner, Rob ; Krstic, Slobodan
Author_Institution :
DRS Power & Control Technol., Milwaukee, WI
fYear :
2005
fDate :
15-15 May 2005
Firstpage :
1423
Lastpage :
1430
Abstract :
Despite the growing proliferation of three level converters, practical design guidelines for these systems are not readily available. This paper describes such design guidelines for the construction and control of three level converters. Loss equations that assist in thermal design and device sizing are provided along with current estimates for sizing link capacitors. The primary commutation mechanisms and the relevant parasitics effects are identified. A low inductance busplane design is presented for designs featuring dual IGBT modules and low inductance snubber capacitor connections are shown. A discussion of the control implementation using a DSP and FPGA platform is provided
Keywords :
design engineering; digital signal processing chips; field programmable gate arrays; insulated gate bipolar transistors; power capacitors; power convertors; snubbers; DSP; FPGA platform; device sizing; dual IGBT modules; inductance busplane design; link capacitors; loss equations; low inductance snubber capacitor; neutral point clamped converters; primary commutation mechanisms; thermal design; three level converters; Capacitors; Circuits; Commutation; Diodes; Equations; Field programmable gate arrays; Guidelines; Inductance; Switching converters; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electric Machines and Drives, 2005 IEEE International Conference on
Conference_Location :
San Antonio, TX
Print_ISBN :
0-7803-8987-5
Electronic_ISBN :
0-7803-8988-3
Type :
conf
DOI :
10.1109/IEMDC.2005.195908
Filename :
1531526
Link To Document :
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