SDMLp: On the use of complementary Pass transistor Logic for design of DPA resistant circuits

The emergence and proliferation of Smart Cards and other security-centric technologies require ongoing advancement in secure-IC design. We propose advanced IC protection from Differential Power Analysis attack though a hybrid-logic style based on Complementary Pass-transistor and Dynamic and Differential Logic (DDL) in conjunction with a synthesis methodology based on Reduced Ordered Binary Decision Diagrams. We demonstrate the capabilities of our logic cell and compare it with Wave Dynamic Differential Logic, and the traditional Standard Complementary Logic (SCMOS). Experimental results on a DES layout show significant reduction in area (43%) and total power (50%) and near constant power consumption in every cycle when compared to existing DDL styles at a speed penalty (20%) against SCMOS.