Constrained specification-based test stimulus generation for analog circuits using nonlinear performance prediction models

The problem of signature-based testing of analog circuits has received a lot of attention in the recent past. In signature-test, a carefully optimized stimulus is applied to the CUT and its specifications are predicted from the test response. This results in test time reduction by 10×-50×. In this paper, a new test generation approach is presented for optimizing a test stimulus that increases the accuracy of specification prediction from the test response. Nonlinear models are used to map the test response to the circuit´s specifications. They are accurate in the regions of the measurement space where the circuit´s specifications are the most sensitive to process perturbations and maximum information about the CUT´s specifications is contained in the observed test response. The test stimulus can be constrained to lie within a specified bandwidth or a specified voltage or current range. This ability is further used to generate wafer-probe and assembled-package tests