t-Private logic synthesis on FPGAs

Author

Jungmin Park ; Tyagi, Akhilesh

Author_Institution

Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA

fYear

2012

fDate

3-4 June 2012

Firstpage

63

Lastpage

68

Abstract

A t-private circuit reveals no information about any internal logic node with up to t probes each cycle. In this paper, we propose efficient t-private logic design schemas. Note that these t probes pose a more powerful adversary than a side-channel attack. We develop tail-recursive t-private circuits based on AND-XOR networks. The tail-recursive t-private circuits are especially well-suited for FPGA LUT implementations. We implement simple adders using t-private tail-recursive logic synthesis on FPGA. Compared to the original t-private circuit model, our model reduces area by 50% and delay by 33% for FPGA implementations.

Keywords

cryptography; field programmable gate arrays; logic design; logic gates; table lookup; AND-XOR networks; FPGA LUT implementations; cryptographic algorithms; t-private logic design schemas; t-private tail-recursive logic synthesis; tail-recursive t-private circuits; Adders; Cryptography; Field programmable gate arrays; Logic gates; Privacy; Probes; Table lookup; FPGA; LUT; probing attack; side-channel attack; t-private circuit;

fLanguage

English

Publisher

ieee

Conference_Titel

Hardware-Oriented Security and Trust (HOST), 2012 IEEE International Symposium on

Conference_Location

San Francisco, CA

Print_ISBN

978-1-4673-2341-3

Type

conf

DOI

10.1109/HST.2012.6224321

Filename

6224321