Title :
GALA approach in design of asynchronous control for counterflow pipeline processor
Author :
Varshavsky, Victor ; Marakhovsky, Vyacheslav
Abstract :
This paper approaches the problem of building an asynchronous control for a stage of the Sproull´s Counterflow Pipeline Processor (CFPP) that does not need arbiters. It is shown that there is no arbitration situations in a synchronous pipeline control circuit with two-track synchronization. An asynchronous control circuit can be built by a synchronous prototype with help of GALA-methodology using the procedure of synchro-stratum designing suggested earlier by the authors [1994-6]
Keywords :
asynchronous circuits; digital signal processing chips; pipeline processing; GALA approach; Sproull´s counterflow pipeline processor; asynchronous control; synchro-stratum designing; synchronous prototype; two-track synchronization; Automata; Buildings; Clocks; Computer architecture; Counting circuits; Master-slave; Pipelines; Prototypes; Registers; Synchronization;
Conference_Titel :
Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on
Conference_Location :
Christchurch
Print_ISBN :
0-7695-1453-7
DOI :
10.1109/DELTA.2002.994592
