Title :
High speed multi-lane LVDS inter-FPGA communication link
Author :
Godbole, Parikshit ; Batth, Anshul ; Ramaswamy, Nandakumar
Author_Institution :
Hardware Technol. Dev. Group, Centre for Dev. of Adv. Comput. (C-DAC), Pune, India
Abstract :
Systems employing multiple FPGAs to handle distributed processing require data communication among FPGAs for unified operation. This paper describes implementation of a multi-lane Low Voltage Differential Signaling (LVDS) interface to form 10 Gbps full duplex communication link interconnecting multiple FPGAs on a board. The design utilizes advanced IO resources available in the latest Virtex and Spartan series of FPGAs from Xilinx. We also developed a Bit Error Rate Tester for evaluating each individual LVDS physical lane operating at 625 Mbps. Challenges involved in the board design, related to implementation of the interface, are also discussed in this paper.
Keywords :
data communication; distributed processing; error statistics; field programmable gate arrays; peripheral interfaces; Spartan series; Virtex series; bit error rate tester; data communication; distributed processing; interconnecting multiple FPGA; multilane LVDS interFPGA communication link; multilane low voltage differential signaling interface; Bit error rate; Clocks; Field programmable gate arrays; Receivers; Synchronization; Training; Transmitters; BERT; FPGA; LVDS; Spartan; Virtex;
Conference_Titel :
Computational Intelligence and Computing Research (ICCIC), 2010 IEEE International Conference on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4244-5965-0
Electronic_ISBN :
978-1-4244-5967-4
DOI :
10.1109/ICCIC.2010.5705808
