Address and data scrambling: causes and impact on memory tests

Author

Van de Goor, Ad J. ; Schanstra, Ivo

Author_Institution

Dept. of Inf. Technol. & Syst., Delft Univ. of Technol., Netherlands

fYear

2002

fDate

2002

Firstpage

128

Lastpage

136

Abstract

The way address sequences and data patterns appear on the outside of a memory may differ from their internal appearance; this effect is referred to as scrambling, which has a large impact on the effectiveness of the used tests. This paper presents an analysis of address and data scrambling for memory chips, at the layout and at the electrical level. A method is presented to determine the data backgrounds to be used for the different memory tests. It will be shown that the required data backgrounds are fault model, and hence, also test specific. Industrial results will show the influence of the used data backgrounds on the fault coverage of the tests

Keywords

fault simulation; integrated circuit layout; integrated circuit modelling; integrated circuit testing; integrated memory circuits; address scrambling; address sequences; data backgrounds; data patterns; data scrambling; electrical level; fault coverage; fault model specific; layout level; memory chips; memory tests; test specific; Cause effect analysis; Data engineering; Design methodology; Electronic switching systems; Fault detection; Hip; Information technology; Logic testing; System testing; Systems engineering and theory;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on

Conference_Location

Christchurch

Print_ISBN

0-7695-1453-7

Type

conf

DOI

10.1109/DELTA.2002.994601

Filename

994601