Title :
A method for storing fail bit maps in burn-in memory testers
Author :
Iseno, Atsumu ; Iguchi, Yukihiro
Author_Institution :
Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan
Abstract :
Although fail bit maps in burn-in memory testers are important for analyzing process problems, we need very large storage for storing them. This paper presented a method for compressing fail bit maps and storing them in cache RAMs. We classify fail patterns under six types. Cache RAM stores the fail types and their locations. Since the proposed method is simple, it can be easily implemented in hardware on every DUT (device under test) board. A prototype has been developed by using an FPGA and an SRAM
Keywords :
cache storage; failure analysis; integrated circuit reliability; integrated circuit testing; life testing; random-access storage; DUT; FPGA; SRAM; burn-in memory testers; cache RAMs; fail bit maps; fail patterns; Computerized monitoring; Condition monitoring; Failure analysis; Field programmable gate arrays; Hardware; Power supplies; Prototypes; Random access memory; Testing; Voltage;
Conference_Titel :
Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on
Conference_Location :
Christchurch
Print_ISBN :
0-7695-1453-7
DOI :
10.1109/DELTA.2002.994603
