Title :
An ECL RISC microprocessor designed for two level cache
Author :
Roberts, David ; Layman, Tim ; Taylor, George
Author_Institution :
MIPS Comput. Syst. Inc., Sunnyvale, CA, USA
fDate :
Feb. 26 1990-March 2 1990
Abstract :
RISC architectures by virtue of their streamlined instruction set and more efficient use of fundamental machine resources are capable of exploiting emerging VLSI technologies more quickly than traditional, more complicated, machine architectures. This paper describes the recently announced MIPS R6000, R6010 and R6020 ECL chip set, which provides further evidence of the validity of this argument.<>
Keywords :
emitter-coupled logic; microprocessor chips; reduced instruction set computing; ECL RISC microprocessor; MIPS R6000; R6010; R6020; machine resources; streamlined instruction set; two level cache; Clocks; Computer architecture; Coupling circuits; Logic; Microprocessors; Read-write memory; Reduced instruction set computing; Registers; System buses; Very large scale integration;
Conference_Titel :
Compcon Spring '90. Intellectual Leverage. Digest of Papers. Thirty-Fifth IEEE Computer Society International Conference.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-2028-5
DOI :
10.1109/CMPCON.1990.63680
