• DocumentCode
    2402107
  • Title

    Standard test bench for optimization and characterization of combinational circuits

  • Author

    Tiwari, Satish Chandra ; Khan, Mohammad Ayoub ; Singh, Kunwar ; Sangal, Ankur

  • Author_Institution
    N.S.I.T., Univ. of Delhi, Delhi, India
  • fYear
    2012
  • fDate
    15-17 March 2012
  • Firstpage
    1
  • Lastpage
    5
  • Abstract
    Choice of a combinational circuit among large number of circuits having same functionality has been always a complex and time consuming task for digital designers. Different circuits (where they are initially proposed) were optimized using different techniques and objectives. Moreover there merits vary as per optimization methodology and technique variations. Hence every time when there is a requirement of particular functionality circuit, choosing best one amongst available circuits requires re-characterization. The paper presents a thorough investigation of existing optimization techniques while presenting their merits and demerits over each other. Based on same, the paper proposes a standard test bench for optimization and characterization of combinational circuits. Finally using the proposed methodology a combinational circuitry has been successfully characterized.
  • Keywords
    combinational circuits; optimisation; combinational circuitry; digital designer; functionality circuit; optimization methodology; standard test bench; Algorithm design and analysis; Application software; Delay; Logic gates; Optimization; SPICE; Transistors; Combinational circuit; Logic Effort; VLSI; low power; optimization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signal Processing, Computing and Control (ISPCC), 2012 IEEE International Conference on
  • Conference_Location
    Waknaghat Solan
  • Print_ISBN
    978-1-4673-1317-9
  • Type

    conf

  • DOI
    10.1109/ISPCC.2012.6224346
  • Filename
    6224346