FPGA implementation of chaotic state sequence generator for secure communication

Author

Chawla, Ginni ; Izharuddin ; Farooq, Omar ; Rafiq, M. Qasim

Author_Institution

Dept. of Electron. Eng., Aligarh Muslim Univ., Aligarh, India

fYear

2012

fDate

15-17 March 2012

Firstpage

1

Lastpage

5

Abstract

In this work, a hardware implementation of Chaotic State Sequence Generator for Secure Communication is proposed. The state of the chaotic generator is quantized by a threshold detector and fed to the 16-bit shift register which stores states at sixteen different time instants. The state selection corresponding to any one of the 16 time instant is performed by a multiplexer in pseudo-random manner using a Finite State Machine. The designs were coded in VHDL, implemented on a FPGA device and successfully tested for image encryption application.

Keywords

chaos generators; cryptography; field programmable gate arrays; finite state machines; hardware description languages; image processing; logic testing; multiplexing equipment; random sequences; shift registers; telecommunication security; 16-bit shift register; FPGA device; VHDL; chaotic state sequence generator; finite state machine; image encryption application; multiplexer; pseudo-random manner; secure communication; state selection; threshold detector; word length 16 bit; Chaotic communication; Encryption; Generators; Hardware; Logic gates; Chaos; Pseudo-random sequence; Secure Communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing, Computing and Control (ISPCC), 2012 IEEE International Conference on

Conference_Location

Waknaghat Solan

Print_ISBN

978-1-4673-1317-9

Type

conf

DOI

10.1109/ISPCC.2012.6224348

Filename

6224348