Title :
The execution pipeline of the Intel i486 CPU
Author_Institution :
Intel Corp., Santa Clara, CA, USA
fDate :
Feb. 26 1990-March 2 1990
Abstract :
The integer instruction execution pipeline of the Intel i486 processor is described. The performance of the i486 CPU in a system is related to several systems based on competitive reduced-instruction-set-computer (RISC) processors. The instruction pipeline was designed to execute instructions at a sustained rate of 1 clock per instruction. A key to achieving this rate was the integration of the cache into the pipeline. Another key was pipelining the instruction decoder into two stages to provide a sustained throughput of 1 instruction per clock, while decoding the complex instruction formats of the Intel 386 family architecture. An overview of the pipeline is provided by giving a brief description of each pipeline stage. Then several multiple instruction examples are given to illustrate some key properties of the pipeline.<>
Keywords :
microprocessor chips; reduced instruction set computing; Intel i486 CPU; decoding; execution pipeline; instruction decoder; integer instruction execution pipeline; performance; reduced-instruction-set-computer; CMOS process; Clocks; Computer architecture; Coprocessors; Decoding; Microcomputers; Pipelines; Plastic packaging; Protection; Software performance;
Conference_Titel :
Compcon Spring '90. Intellectual Leverage. Digest of Papers. Thirty-Fifth IEEE Computer Society International Conference.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-2028-5
DOI :
10.1109/CMPCON.1990.63682
