The i486 microprocessor integrated cache and bus interface

The Intel i486 microprocessor includes an integrated 8-kB combined instruction and data cache. The cache, how its parameters were determined, how it fits into the i486 microprocessor pipeline, and the implications of the integrated cache on the i486 microprocessor bus interface are described. The cache must provide software-transparent memory consistency, in addition to supporting self-modifying code. The first cache parameter that needs to be determined is the cache size. The larger the cache in the system, the higher the hit ratio, and therefore the greater the performance improvement in the system. With the cache size set, the next parameter to set is the line size. The line size is the amount of information placed into the cache whenever a cache miss occurs. Previous cache studies show that longer cache lines produce greater hit ratios at the expense of larger miss penalties. The tradeoff between these two figures for optimal performance is heavily dependent on the nature of the memory-to-cache interface. The next cache parameter to be set is the associativity of the cache. The associativity determines the number of places a particular memory location can be placed in the cache. With the nature of the bus defined, the parameters chosen for the cache organization were evaluated.<>