Title :
2 GHz low power double edge triggered flip-flop in 65nm CMOS technology
Author :
Khan, Iqbal A. ; Shaikh, D. ; Beg, M.T.
Author_Institution :
Deptt of Elect & Comm, Jamia Millia Islamia, New Delhi, India
Abstract :
This paper proposed a low power, Double-edge-triggered flip-flop design in 65nm CMOS technology. The proposed DETFF is having fewer clocked transistors than earlier conventional designs. The DETFF is simulated with different clock frequencies ranging from 400MHz to 2GHz. Simulation results show least delay, lowest power dissipation than older designs. Further, at scaled voltages the average power dissipation is improved by 46.85% and 96.60% when compared with DETFF1 and DETFF2 respectively and improvement in PDP is 58% and 97.54% as compared to DETFF1 and DETFF2 respectively, which claims that proposed design is suitable for low power, low voltage and high speed applications.
Keywords :
CMOS integrated circuits; flip-flops; CMOS technology; DETFF; average power dissipation; clock frequency; clocked transistors; frequency 400 MHz to 2 GHz; low power double edge triggered flip flop design; size 65 nm; Clocks; Delay; Flip-flops; Integrated circuit modeling; Logic gates; Power demand; Transistors; CMOS; Double-edge-triggered; delay; flip-flops; power dissipiation;
Conference_Titel :
Signal Processing, Computing and Control (ISPCC), 2012 IEEE International Conference on
Conference_Location :
Waknaghat Solan
Print_ISBN :
978-1-4673-1317-9
DOI :
10.1109/ISPCC.2012.6224375
