2 GHz low power double edge triggered flip-flop in 65nm CMOS technology

This paper proposed a low power, Double-edge-triggered flip-flop design in 65nm CMOS technology. The proposed DETFF is having fewer clocked transistors than earlier conventional designs. The DETFF is simulated with different clock frequencies ranging from 400MHz to 2GHz. Simulation results show least delay, lowest power dissipation than older designs. Further, at scaled voltages the average power dissipation is improved by 46.85% and 96.60% when compared with DETFF1 and DETFF2 respectively and improvement in PDP is 58% and 97.54% as compared to DETFF1 and DETFF2 respectively, which claims that proposed design is suitable for low power, low voltage and high speed applications.