Design and implementation of Reed Solomon Decoder for 802.16 network using FPGA

This paper presents a design and FPGA implementation of a reconfigurable FEC Decoder based on Reed Solomon Code for WiMax Network. The implementation, written in Very High Speed hardware description Language (VHDL) is based on Berlekamp Massey, Forney and Chein Algorithm. The 802.16 network standard recommends the use of Reed-Solomon code RS (255,239), which is implemented and discussed in this paper. It is targeted to be applied in a forward error correction system based on 802.16 network standard to improve the overall performance of the system. The objective of this work is to implement a Reed-Solomon VHDL code to measure the performance of the RS Decoder on Xilinx Virtex II pro (xc2vp50-5-ff1148) and Xilinx Spartan 3e (xc3s500e-4-fg320) FPGA. The performance of the implemented RS codec on both FPGAs will be compared. The performance metrics to be used are the area occupied by the design and the speed at which the design can run.