Dynamic CMOS circuit techniques for delay and power reduction in parallel adders

Author

Lindkvist, Hans ; Andersson, Per

Author_Institution

Dept. of Comput. Eng., Lund Univ., Sweden

fYear

1995

fDate

27-29 Mar 1995

Firstpage

121

Lastpage

130

Abstract

The successful design of high-speed parallel adders depend mainly on fast calculation of carry signals. A technique based on combining Manchester-Carry chains (MCC) with Clock-and-Data pre-charged dynamic logic blocks (CDPD) is suggested and analysed. This technique, as well as pure MCC and CDPD techniques, was incorporated into the design of carry calculation trees. Simulations indicate that 11-25% decrease of delay at the same time as a 19-29% reduction of power consumption is made possible by combining MCCs with CDPD gates instead of using trees consisting solely of either MCCs of CDPD gates

Keywords

CMOS logic circuits; VLSI; adders; carry logic; delays; digital arithmetic; logic design; parallel processing; Manchester-carry chains; carry calculation trees; clock/data precharged dynamic logic blocks; delay reduction; dynamic CMOS circuit techniques; high-speed adders; parallel adders; power consumption; power reduction; Adders; CMOS logic circuits; CMOS technology; Clocks; Concurrent computing; Delay; Logic design; Signal generators; Space technology; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Research in VLSI, 1995. Proceedings., Sixteenth Conference on

Conference_Location

Chapel Hill, NC

Print_ISBN

0-8186-7074-9

Type

conf

DOI

10.1109/ARVLSI.1995.515615

Filename

515615