Complementary GaAs junction-gated heterostructure field effect transistor technology

Author

Baca, A.G. ; Zolper, J.C. ; Sherwin, M.E. ; Robertson, P.J. ; Shul, R.J. ; Howard, A.J. ; Rieger, D.J. ; Klem, J.F.

Author_Institution

Sandia Nat. Labs., Albuquerque, NM, USA

fYear

1994

fDate

16-19 Oct. 1994

Firstpage

59

Lastpage

62

Abstract

The first circuit results for a new GaAs complementary logic technology are presented. The technology allows for independently optimizable p- and nchannel transistors with junction gates. Excellent loaded gate delays of 179 ps at 1.2 V and 319 ps at 0.8 V have been demonstrated at low power supply voltages. A power-delay product of 8.9 fJ was obtained at 0.8 V.

Keywords

III-V semiconductors; JFET integrated circuits; field effect logic circuits; gallium arsenide; integrated circuit technology; 0.8 to 1.2 V; 179 to 319 ps; GaAs; GaAs junction-gated heterostructure field effect transistor; complementary logic technology; loaded gate delays; low power supply voltages; n-channel transistors; p-channel transistors; power-delay product; CMOS logic circuits; Epitaxial layers; Gallium arsenide; HEMTs; Indium gallium arsenide; Integrated circuit technology; Logic circuits; MODFETs; Tungsten; Wet etching;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1994. Technical Digest 1994., 16th Annual

Conference_Location

Phildelphia, PA, USA

ISSN

1064-7775

Print_ISBN

0-7803-1975-3

Type

conf

DOI

10.1109/GAAS.1994.636920

Filename

636920