Hybrid modified booth encoded algorithm-carry save adder fast multiplier

Author

Daud, Nik Ghazali Nik ; Hashim, F.R. ; Mustapha, Muhazam ; Badruddin, M.S.

Author_Institution

Dept. of Electr. & Electron. Eng., Univ. Pertahanan Nasional Malaysia, Kuala Lumpur, Malaysia

fYear

2014

fDate

17-18 Nov. 2014

Firstpage

1

Lastpage

6

Abstract

One of the effective ways to speed up multiplication are by reducing the number of partial products and accelerating the accumulation. In this paper, a new architecture of hybrid Modified Booth Encoded Algorithm (MBE) and Carry Save Adder (CSA) is developed as fast multiplier architecture. Altera Quartus II platform is used to run the simulation. The architecture design is programmed into FPGA using Altera DE2 board to verify the synthesizability on physical hardware. This hybrid fast multiplier delivers good performance in term of higher speed as well as in term of less usage of logic elements.

Keywords

adders; field programmable gate arrays; Altera DE2 board; Altera Quartus II platform; CSA; FPGA; MBE; architecture design; carry save adder; fast multiplier architecture; field-programmable gate array; hybrid modified booth encoded algorithm; physical hardware; Decision support systems; Carry Save Adder; Fast Multiplier; Modified Booth Algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Information and Communication Technology for The Muslim World (ICT4M), 2014 The 5th International Conference on

Conference_Location

Kuching

Type

conf

DOI

10.1109/ICT4M.2014.7020607

Filename

7020607