A 590,000 transistor 48,000 pixel, contrast sensitive, edge enhancing, CMOS imager-silicon retina

Author

Andreou, Andreas G. ; Boahen, Kwabena A.

Author_Institution

Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA

fYear

1995

fDate

27-29 Mar 1995

Firstpage

225

Lastpage

240

Abstract

We present an experimental analog VLSI focal plane processor for the phototransduction, local gain control and edge enhancement of natural images. The single chip system incorporates 590,000 transistors in 48,000 pixels, and it has been fabricated on a 9.5×9.3 mm die in a 1.2 μm n-well double metal, double poly, digital oriented CMOS technology. The organization of the system abstracts from the structure and function of the vertebrate distal retina. The adopted design style, current-mode subthreshold CMOS using circuits of minimal complexity offers the possibility of ultra low power dissipation and area efficiency, commensurate with VLSI integration

Keywords

CMOS integrated circuits; VLSI; computer vision; edge detection; focal planes; image sensors; 1.2 micron; 48000 pixel; CMOS imager; analog VLSI focal plane processor; area efficiency; contrast; current-mode subthreshold CMOS; edge enhancement; local gain control; n-well double metal double poly digital oriented CMOS technology; phototransduction; silicon retina; single chip system; ultra low power dissipation; vertebrate distal retina; CMOS image sensors; CMOS technology; Cameras; Dynamic range; Gain control; Information technology; Lighting; Pixel; Robot vision systems; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Research in VLSI, 1995. Proceedings., Sixteenth Conference on

Conference_Location

Chapel Hill, NC

Print_ISBN

0-8186-7074-9

Type

conf

DOI

10.1109/ARVLSI.1995.515623

Filename

515623