On the performance of level-clocked circuits

Although it is well-known that substituting level-sensitive latches for edge-triggered registers can boost circuit performance, results of measuring the performance gained by using latches in real circuits-when retiming is used to optimize the performance of both types of circuits-have been disappointing. In this paper we re-examine the speedup that can be expected from using latches and develop upper and lower bounds on the clock period of retimed circuits that are tighter than previously published bounds. We then show experimentally that pipelined level-clocked circuits almost always achieve the lower bound while edge-clocked circuits seldom do. These bounds also illuminate where performance from level-clocking can and cannot be achieved. For the circuits that do benefit from latches, the average speedup is about 11%, although much greater speedups are common. Another factor affecting performance that has generally been ignored is clock skew. Clocks in edge-clocked circuits must be slowed down by an amount equal to the clock skew while level-clocked circuits are more tolerant of clock skew. We show experimentally that on average level-clocked circuits can tolerate clock skew of 15% of the clock period which can be translated directly into increased performance