PLL phase error and power supply noise [microprocessors]

Author

Eckhardt, J.P. ; Jenkins, K.A.

Author_Institution

IBM Corp., Poughkeepsie, NY, USA

fYear

1998

fDate

26-28 Oct 1998

Firstpage

73

Lastpage

76

Abstract

Phase error in phase-locked loops (PLLs) in microprocessor systems is discussed. The distinction between jitter, or random phase error, and systematic accumulated phase error is explained. Accumulated phase error is caused by disturbances of the power supply voltages. Even a short disturbance can lead to a phase error which persists and accumulates over many clock cycles. A system which creates controlled power supply noise and measures the PLL response is described. Examples are shown using the PLL of a 400 MHz S/390 microprocessor

Keywords

clocks; driver circuits; error analysis; integrated circuit measurement; integrated circuit noise; integrated circuit reliability; jitter; microprocessor chips; phase locked loops; 400 MHz; PLL; PLL phase error; PLL response measurement; PLLs; S/390 microprocessor; accumulated phase error; clock cycles; controlled power supply noise; jitter; microprocessor system; microprocessors; phase error; phase-locked loops; power supply noise; power supply voltage disturbance; random phase error; systematic accumulated phase error; Clocks; Control systems; Jitter; Microprocessors; Noise measurement; Phase locked loops; Phase noise; Power measurement; Power supplies; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 1998. IEEE 7th Topical Meeting on

Conference_Location

West Point, NY

Print_ISBN

0-7803-4965-2

Type

conf

DOI

10.1109/EPEP.1998.733753

Filename

733753