Optimized polysilicon CMOS technology for gate array applications

The gate arrays option in manufacturing ASIC CMOS is conditioned by the possibility of satisfying small orders requirements of small- and medium-sized electronic equipment manufacturing companies, in a large variety of circuits. The authors present contributions in optimizing critical processes for an n-well CMOS polysilicon gate arrays technology. Technological achievements were proved by measurements on the test devices but mainly by array chip fabrication. There were manufactured chips for specialized circuits intended for telephone switching equipment