A novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19 Gb/s decision circuit using 0.2 /spl mu/m GaAs MESFET

Author

Murata, K. ; Otsuji, T. ; Ohhata, M. ; Togashi, M. ; Sano, E. ; Suznki, M.

Author_Institution

NTT Transmission Syst. Labs., Kanagawa, Japan

fYear

1994

fDate

16-19 Oct. 1994

Firstpage

193

Lastpage

196

Abstract

This paper describes a novel high-speed flip-flop circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs SCFL Logic. We reveal the high-speed operation mechanism of HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series gated master slave flip-flops and HLO-FFs based on these expressions is also proposed. A SPICE simulation and the fabrication of two decision ICs confirm the accuracy of our analytical method and the high speed operation of a HLO-FF decision circuit at 19 Gb/s.

Keywords

III-V semiconductors; MESFET integrated circuits; SPICE; decision circuits; field effect logic circuits; flip-flops; gallium arsenide; 0.2 micron; 19 Gbit/s; GaAs; GaAs MESFET ICs; HLO-FF circuit; SCFL logic; SPICE simulation; decision circuit; design methodology; fabrication; high-speed latching operation flip-flop; propagation delay time; series gated master slave flip-flop; Analytical models; Circuit simulation; Design methodology; Flip-flops; Gallium arsenide; Logic circuits; MESFET circuits; Master-slave; Propagation delay; SPICE;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1994. Technical Digest 1994., 16th Annual

Conference_Location

Phildelphia, PA, USA

ISSN

1064-7775

Print_ISBN

0-7803-1975-3

Type

conf

DOI

10.1109/GAAS.1994.636965

Filename

636965