Redundancy for yield enhancement in the 3-D computer

A prototype 3-D Computer which demonstrates the feasibility of the stacked wafer approach is discussed. The wafer-scale integrated circuits of the 3-D Computer have been carefully partitioned to enable redundancy to be used to insure high yields. Redundancy approaches, implementation issues, and testability both for the schemes used in the prototype and in future generations of the 3-D Computer are discussed. The circuits of the 32×32 array processor used 100% interstitial redundancy using one-way connectivity. The 128×128 array processor now underway construction, as well as a future larger array processor, use a mixture of redundancy schemes: a 50% redundancy with four-way connectivity for the array logic and 100% redundancy for the nearest-neighbor communication and control circuits. The 50% redundancy minimizes the area and test overhead for sparing while improving yields