DocumentCode
2404694
Title
High-Level Design Strategies for Architectural Synthesis
Author
Wehn, Norbert ; Payer, Michael
Author_Institution
Siemens Corp. R&D, Darmstadt Univ. of Technol., Munich, Germany
fYear
1992
fDate
21-23 Sept. 1992
Firstpage
61
Lastpage
70
Abstract
In this paper we give an overview of state-of-the-art high-level design strategies. We introduce formal definitions of the terms high-level synthesis, behavioral synthesis, architectural synthesis, and register-transfer level synthesis. These definitions allow us to classify specification languages and synthesis systems. Furthermore, we discuss essential issues such as the impact of high-level synthesis on industrial design practice, modeling of the design space, the role of VHDL, and the hardware specification problem. To demonstrate different synthesis philosophies, we present the three synthesis systems CATHEDRAL, HIS, and CALLAS as typical examples. Each of these systems is intended for a different application domain, namely CATHEDRAL for digital signal processing algorithms, HIS for processor structures, and CALLAS for control-dominated designs.
Keywords
hardware description languages; high level synthesis; CALLAS; CATHEDRAL; HIS; VHDL; architectural synthesis; behavioral synthesis; control-dominated designs; design space modelling; digital signal processing algorithms; hardware specification problem; high-level design strategy; industrial design practice; processor structures; register-transfer level synthesis; specification language classification; Aerospace industry; Control system synthesis; Control systems; Digital signal processing; Hardware; High level synthesis; Signal design; Signal processing algorithms; Signal synthesis; Specification languages;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1992. ESSCIRC '92. Eighteenth European
Conference_Location
Copenhagen
Print_ISBN
87-984232-0-7
Type
conf
DOI
10.1109/ESSCIRC.1992.5468448
Filename
5468448
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