Generating formal models for real-time verification by exact low-level runtime analysis of synchronous programs

Synchronous programming languages are well-suited for the implementation and verification of real-time systems. The main benefit for the estimation of real-time constraints is thereby that the macro steps provided by synchronous programs can be directly used for runtime analysis. If synchronous circuits are generated from these descriptions, the macro steps are implemented by combinatorial circuits, and if software is generated, they correspond to basic building blocks that do not contain loops. In this paper, we describe methods to generate timed transitions systems from a synchronous program by taking the final architecture into account. For software synthesis, this requires considering different microprocessors and compilers, and for hardware synthesis, this requires considering a hierarchy of clocks to optimize the clock speed.