A 1.0-nsec 32-bit prefix tree adder in 0.25-μm static CMOS

The carries in a carry-lookahead adder can be computed by using a separate prefix tree for each bit location. This is nearly twice as fast as in the standard Brent and Kung technique. We show that the primary carry input signal can be incorporated into the prefix trees without additional delay. This new architechture reduces the logic depth of the n-bit adder by 1. This technique is not limited to radix-2 adder trees. Using fully-static circuits, a 32-bit radix-2 prefix tree adder has a delay of 1.0 nsec in the Lucent 0.25-μm CMOS technology