VHDL implementation of 2-D median filter

Author

Palaniswamy, Krishna J. ; Rizkalla, Maher E. ; Sinha, Akhomri C. ; El-Sharkawy, MoEiamed ; Salama, Paul

Author_Institution

Dept. of Electr. Eng., Indiana Univ., Indianapolis, IN, USA

Volume

2

fYear

1999

fDate

1999

Firstpage

744

Abstract

An 8-bit VHDL based 2-D median filter is designed using Mentor Graphics tools. The algorithm is based on sorting pixel samples and extracting their median values. The VHDL code was written, synthesized and optimized for an IC layout using CMOS 2micron technology. A MatLab program for this algorithm was written, tested and verified on several 400×400 images. The paper details the algorithm and CAD tool processing. This paper is considered as a building block for the development of post-processing Application Specific Integrated Circuits (ASIC) base system for video decompressed signals

Keywords

CMOS digital integrated circuits; circuit layout CAD; hardware description languages; integrated circuit layout; median filters; two-dimensional digital filters; 2 micron; 2D median filter; 8 bit; ASIC; CAD tool; CMOS IC layout; MatLab program; Mentor Graphics; VHDL code; design algorithm; image processing; video signal decompression; Application specific integrated circuits; CMOS integrated circuits; CMOS technology; Circuit testing; Filters; Graphics; Integrated circuit layout; Integrated circuit synthesis; Integrated circuit technology; Sorting;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. 42nd Midwest Symposium on

Conference_Location

Las Cruces, NM

Print_ISBN

0-7803-5491-5

Type

conf

DOI

10.1109/MWSCAS.1999.867744

Filename

867744