Design of asynchronous controllers with delay insensitive interface

Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behavior Asynchronous speed-independent (SI) circuits, whose behavior is only robust to gate delay variations, may be too optimistic. On the other hand, building circuits totally delay-insensitive (DI), for both gates and wires, is impractical. The paper presents a new approach for synthesis of globally DI and locally SI circuits suggested by Hiroshi Saito et al. (1999). The method starts from a speed-independent implementation and locally modifies gate functions to ensure their independence from delays in communication wires. The suggested approach was successfully tested on a set of benchmarks