Performance assessment of scaled strained-Si channel-on-insulator (SSOI) CMOS

Strained-Si channel devices have recently become of interest for future high-performance applications due to higher carrier mobility and preservation of conventional device structure/geometry. One important feature in the strained-Si devices is the heterostructural band offset in the channel and buffer layer, which reduces V_t, thereby increasing I_off. We assess the circuit performance of strained-Si devices including SSOI via a physics-based circuit model calibrated against fabricated 70 nm strained and unstrained (control) devices. Device design point and performance projection and trade-off are presented, thus allowing exploitation of maximum performance in the strained-Si devices.