Title :
Register transfer operation analysis during data path verification
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
Abstract :
A control part-data path partition based sequential circuit verification scheme aimed at avoiding state explosion comprises two major modules namely, a data path verifier and a control part verifier. The functional specifications of these modules have been identified. Of the two broad tasks involved in data path verification, namely status condition analysis and register transfer operation analysis, a method for the second task along with its termination, soundness and completeness have been treated rigorously. Its performance on some data path architectures has been reported
Keywords :
formal verification; high level synthesis; logic partitioning; sequential circuits; control part verifier; control part-data path partition; data path verifier; register transfer operation analysis; sequential circuit verification; state explosion; status condition analysis; Computer science; Data analysis; Data engineering; Data mining; Explosions; Integrated circuit interconnections; Memory; Registers; Sequential circuits; Signal analysis;
Conference_Titel :
Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
Conference_Location :
Bangalore
Print_ISBN :
0-7695-1441-3
DOI :
10.1109/ASPDAC.2002.994914
