DocumentCode
2405867
Title
Switching activity estimation of large circuits using multiple Bayesian networks
Author
Bhanja, Sanjukta ; Ranganathan, N.
Author_Institution
Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
fYear
2002
fDate
2002
Firstpage
187
Lastpage
192
Abstract
Switching activity estimation is a crucial step in estimating dynamic power consumption in CMOS circuits. In this work, we propose a new strategy for efficient segmentation of large circuits so that they can be mapped to Multiple Bayesian Networks (MBN). The goal here is to achieve higher accuracy while reducing the memory requirements during the computation. In order to capture the correlations among the boundaries of segments, a tree dependent (TD) distribution is proposed between the segment boundaries such that the TD distribution is closest to the actual distribution of switching variable with some distance criterion. We use a Maximum Weight Spanning Tree (MWST) based approximation using mutual information between two variables at the boundary as the weight of the edge between the variables. Experimental results for ISCAS´85 circuits show that the proposed method improves accuracy significantly over other methods
Keywords
CMOS digital integrated circuits; belief networks; combinational switching; directed graphs; integrated circuit design; integrated circuit modelling; trees (mathematics); ISCAS´85 circuits; LIDAG structure; combinational circuit; directed acyclic graph; dynamic power consumption; large CMOS circuits; large circuit segmentation; maximum weight spanning tree based approximation; memory requirements; multiple Bayesian networks; switching activity estimation; switching probability model; switching variable distribution; tree-dependent distribution; Bayesian methods; Circuit simulation; Computer science; Energy consumption; Microelectronics; Power engineering and energy; Probability; Semiconductor device modeling; Statistics; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
Conference_Location
Bangalore
Print_ISBN
0-7695-1441-3
Type
conf
DOI
10.1109/ASPDAC.2002.994917
Filename
994917
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